1. Field of the Invention
The present invention relates to a bit synchronization apparatus for recovering high speed NRZ (non-return to zero) data.
2. Description of the Prior Art
The data recovering apparatus had been mainly used in the transmission field at first, but recently, it came to be used for block-to-block connections and chip-to-chip connections.
In the conventional data recovering apparatus, the NRZ data are recovered by using a phase-locked loop (PLL) in which a phase detector is employed for directly comparing the transition phase of the inputting data with the transition phase of clock pulses outputted from a voltage control oscillator. (C. R. Hogge, "A SELF CORRECTING CLOCK RECOVERY CIRCUIT", J. Lightwave technology, vol. LT-3, No. 4, pp 1312-1314, Dec. 1985; and B. Lai and R. C. Walker, A MONOLITHIC 622 Mbps "CLOCK EXTRACTION DATA RETIMING CIRCUIT", ISSCC Digest Tech.
Papers, pp 144-145, Feb 1991).
However, if the bit speed of the NRZ data becomes high, then the output pulse width of a charge-pump and a phase detector of the phase-locked loop (PLL) becomes too small, with the result that the PLL cannot carry out he bit synchronization function in a perfect manner.
In the conventional NRZ data recovering circuit, the output clock pulses of the voltage control oscillator are directly used in a phase comparator without carrying out a frequency division. Therefore, the speed of the recoverable NRZ data is decided by the operating speed of the charge-pump circuit and the phase detector of the PLL.
Generally, however, the charge-pump circuits and the phase detectors have relatively complicated constitutions. Consequently, they are limited in their operating speed, and therefore, the high speed NRZ data recovery becomes difficult.